Asynchronous

这都已经跳票了至少半个decade

No clk, no period, power-efficient, no need to synchronize all parts, no need to overclock

Implementation ideas

Signal: purely functional & with side-effect

Example: And Gate

(pesude code)

module and (
  input reset,
  input bit1high,
  input bit1low,
  input bit2high,
  input bit2low,
  output reg out1high,
  output reg out1low);

  reg previous_bit1high;
  reg previous_bit1low;
  reg previous_bit2high;
  reg previous_bit2low;

  assign input_done = ((bit1high != previous_bit1high) || (bit1low != previous_bit1low)) && ((bit2high != previous_bit2high) || (bit2low != previous_bit2low));
  assign input_1 = bit1high != previous_bit1high;
  assign input_2 = bit2high != previous_bit2high;

  always @(posedge reset, posedge input_done) begin
    if (reset) begin
      {out1high, out1low, previous_bit1high, previous_bit1low, previous_bit2high, previous_bit2low} <= {0, 0, bit1high, bit1low, bit2high, bit2low};
    end else if (input_done) begin
      if (input_1 && input_2) begin
        out1high <= ~out1high;
      end else begin
        out1low <= ~out1low;
      end
      {previous_bit1high, previous_bit1low, previous_bit2high, previous_bit2low} <= {bit1high, bit1low, bit2high, bit2low};
    end
  end

endmodule

Snapshot input: purely functional

Copy input or use reversible logic gate for user to check whether the computing is finished or not

TODO: verilog and/or physics may break the semantics

Of course it would break if some wires are too long.

Usage: reset inputs; wait snapshots to become zero; input; wait snapshots

Example: And Gate

(pesude code)

module and (
  input bit1,
  input bit2,
  output out1,
  output snapshot_bit1,
  output snapshot_bit2);

  always @(bit1, bit2) begin
    {snapshot_bit1, snapshot_bit2, out1} <= {bit1, bit2, bit1 && bit2};
  end

endmodule

A safer version?

(pesude code)

module and (
  input bit1,
  input bit2,
  output reg out1,
  output reg snapshot_bit1,
  output reg snapshot_bit2);

  always @(bit1, bit2) begin
    out1 = bit1 && bit2;
    {snapshot_bit1, snapshot_bit2} <= {bit1, bit2};
  end

endmodule

Dual-Rail

Mutual NOT (01/10)

Valid / Invalid: purely functional & with side-effect

User:

Make Input invaild
Wait Output to be invalid
Input
Wait Output

(pesude code)

module and (
  input bit1high,
  input bit1low,
  input bit2high,
  input bit2low,
  output reg out1high,
  output reg out1low);

  assign input_invalid = !(bit1high || bit1low || bit2high || bit2low);
  assign input_valid = (bit1high != bit1low) && (bit2high != bit2low);

  assign result = bit1high && bit2high;

  always @(posedge input_invalid, posedge input_valid) begin
    if (input_invalid) begin
      {out1high, out1low} <= {0, 0};
    end else if (input_valid) begin
      {out1high, out1low} <= {result, !result};
    end
  end

endmodule

TODO: implement working asynchronous ARM/RISC CPU

Multiple instances of modules of pipeline & Lightweight thread (a scheduler will be needed)

the number of cores? give software a random number

Clock rate? tell software that the frequency is 10Ghz

Inner